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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
DESCRIPTION
The PLS153 and PLS153A are two-level logic elements, consisting of 42 AND gates and 10 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 8 inputs (I) and 10 bidirectional I/O lines (B). These yield variable I/O gate configurations via 10 direction control gates (D), ranging from 18 inputs to 10 outputs. On-chip T/C buffers couple either True (I, B) or Complement (I, B) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Their output polarity, in turn, is individually programmable through a set of EX-OR gates for implementing AND/OR or AND/NOR logic functions. The PLS153 and PLS153A are field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment.
FEATURES
* Field-Programmable (Ni-Cr links) * 8 inputs * 42 AND gates * 10 OR gates * 10 bidirectional I/O lines * Active-High or -Low outputs * 42 product terms:
- 32 logic terms - 10 control terms
PIN CONFIGURATIONS
N Package
I0 I1 I2 I3 I4 I5 I6 I7 B0 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC B9 B8 B7 B6 B5 B4 B3 B2 B1
* I/O propagation delay:
- PLS153: 40ns (max) - PLS153A: 30ns (max)
GND 10
* Input loading: -100A (max) * Power dissipation: 650mW (typ) * 3-State outputs * TTL compatible
APPLICATIONS
N = Plastic DIP (300mil-wide)
A Package
I2 3 I3 I4 I5 I6 I7 4 5 6 7 8 9 10 11 12 13 I1 2 I0 VCC B9 1 20 19 18 17 16 15 14 B8 B7 B6 B5 B4
* Random logic * Code converters * Fault detectors * Function generators * Address mapping * Multiplexing
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In-Line, 300mil-wide 20-Pin Plastic Leaded Chip Carrier ORDER CODE PLS153N, PLS153AN PLS153A, PLS153AA
B0 GND B1 B2 B3
A = Plastic Leaded Chip Carrier
SP00274
DRAWING NUMBER 0408B 0400E
October 22, 1993
1
853-0311 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
LOGIC DIAGRAM
(LOGIC TERMS-P) I0 I1 I2 I3 I4 I5 I6 I7 1 2 3 4 5 6 7 8 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
(CONTROL TERMS)
S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 87 0 X0 S8 S7 S6 S5 S4 S3 S2 S1 S0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 19 B9 18 B8 17 B7 16 B6 15 B5 14 B4 13 B3 12 B2 11 B1 9 B0
NOTES: 1. All programmed `AND' gate locations are pulled to logic "1". 2. All programmed `OR' gate locations are pulled to logic "0". 3. Programmable connection.
SP00276
October 22, 1993
2
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
FUNCTIONAL DIAGRAM
P31 I0 P0 D0 D9
I7 B0
B9
S9 X9
B9
S0 X0
B0
SP00277
ABSOLUTE MAXIMUM RATINGS1
RATINGS SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Operating temperature range Storage temperature range 0 -65 -30 MIN MAX +7 +5.5 +5.5 +30 +100 +75 +150 UNIT VDC VDC VDC mA mA C C
NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 22, 1993
3
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
LOGIC FUNCTION
TYPICAL PRODUCT TERM: Pn = A B C D . . .
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C
TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY = H Z = P0 + P1 + P2 . . . AT OUTPUT POLARITY = L Z = P0 + P1 + P2 + . . . Z = P0 P1 P2 . . .
NOTES: 1. For each of the 10 outputs, either function Z (Active-High) or Z (Active-Low) is available, but not both. The desired output polarity is programmed via the Ex-OR gates. 2. Z, A, B, C, etc. are user defined connections to fixed inputs (I) and bidirectional pins (B). SP00275
The PLS153/A devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook.
DC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75V VCC 5.25V LIMITS SYMBOL Input voltage2 VIL VIH VIC Output Low High Clamp3 voltage2 VCC = MIN VOL VOH Input Low4 High5 current9 VCC = MAX IIL IIH Low High VIN = 0.45V VIN = 5.5V VCC = MAX IO(OFF) IOS ICC Capacitance VCC = 5V CIN CB Input I/O VIN = 2.0V VB = 2.0V 8 15 pF pF Hi-Z state8 VOUT = 5.5V VOUT = 0.45V Short circuit3, 5, 6 VCC supply current7 VOUT = 0V VCC = MAX -15 130 80 -140 -70 155 mA mA A -100 40 A A IOL = 15mA IOH = -2mA 2.4 0.5 V V VCC = MIN VCC = MAX VCC = MIN, IIN = -12mA 2.0 -0.8 -1.2 0.8 V V V PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT
Output current
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with +10V applied to I7. 5. Measured with +10V applied to I0-7. Output sink current is supplied through a resistor to VCC. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with I0, I1 at 0V, I2 - I7 and B0-9 at 4.5V. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 - I7).
October 22, 1993
4
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
AC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75V VCC 5.25V, R1 = 300, R2 = 390 LIMITS SYMBOL PARAMETER FROM TO TEST CONDITION tPD tOE tOD Propagation delay Output enable2 Output disable2 Input Input Input Output Output - Output + CL = 30pF CL = 30pF CL = 5pF MIN PLS153 TYP1 30 25 25 MAX 40 35 35 MIN PLS153A TYP1 20 20 20 MAX 30 30 30 ns ns ns UNIT
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORMS
+3.0V 90%
TIMING DEFINITIONS
SYMBOL tPD
10%
PARAMETER Propagation delay between input and output. Delay between input change and when output is off (Hi-Z or High). Delay between input change and when output reflects specified output level.
0V 5ns +3.0V 90% tR tF 5ns
tOD
tOE
10% 0V 5ns 5ns
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
SP00017
TEST LOAD CIRCUIT
VCC +5V S1
C1
C2 I0 BY
R1
INPUTS
I7 BW
DUT
R2
CL
BX
GND
BZ
OUTPUTS
NOTE: C1 and C2 are to bypass VCC to GND.
SP00278
October 22, 1993
5
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
TIMING DIAGRAM
+3V I, B 1.5V 1.5V 1.5V 0V
VOH B 1.5V VT tOD tOE 1.5V VOL tPD
SP00279
LOGIC PROGRAMMING
The PLS153/A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP, Data I/O's ABELTM and Logical Devices, Inc. CUPLTM design software packages. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLS153/A logic designs can also be generated using the program table entry format detailed on the following page. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/ Software Support) of this data handbook for additional information
OUTPUT POLARITY - (B)
S B X X S B
ACTIVE LEVEL HIGH1 (NON-INVERTING)
CODE H
ACTIVE LEVEL LOW
CODE L
(INVERTING)
SP00280
AND ARRAY - (I, B)
I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B
P, D STATE INACTIVE1, 2 CODE O STATE I, B
P, D CODE H STATE I, B
P, D CODE L STATE DON'T CARE
P, D CODE -
SP00281
ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.
October 22, 1993
6
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
OR ARRAY - (B)
P S P S
Pn STATUS ACTIVE1
CODE A
Pn STATUS INACTIVE
CODE
*
SP00282
NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the True and Complement of an input (either I or B) are left intact.
CAUTION: PLS153A TEST COLUMNS
The PLS153A incorporates two columns not shown in the logic block diagram. These columns are used for in-house testing of the device in the unprogrammed state. These columns must be disabled prior to using the PLS153A in your application. If you are using a Philips Semiconductors-approved programmer, the disabling is accomplished during the device programming sequence. If these columns are not disabled, abnormal operation is possible. Furthermore, because of these test columns, the PLS153A cannot be programmed using the programmer algorithm for the PLS153.
VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs.
October 22, 1993
7
AND ACTIVE B(0) All AND gates are pulled to a logic "0" (Low). Output polarity is non-inverting. A NOTES In the unprogrammed state:
October 22, 1993
OR
CUSTOMER NAME PURCHASE ORDER # PHILIPS DEVICE # CUSTOMER SYMBOLIZED PART # TOTAL NUMBER OF PARTS PROGRAM TABLE #
9 8 7 6 5 4 3 2 1 0 11 15 14 13 12 10
INACTIVE INACTIVE
0
I, B CONTROL HIGH LOW L (POL) H
H
CF(XXXX)
PROGRAM TABLE
I, B
L
I, B(I)
DON'T CARE
--
Unused I and B bits in the AND array should be programmed as Don't Care (-). Unused product terms in the OR array should be programmed as INACTIVE (o).
REV
DATE
T E R M
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
PIN
VARIABLE NAME
7
Programmable logic arrays (18 x 42 x 10)
Philips Semiconductors Programmable Logic Devices
8
7
6
6
5
5
4 I 3
4
3
2
2
1
1
0 AND 9 8
19 18 17 16 15 14 13 12 11
8
7 6 5 4 3 2 1 0 B(I)
9
9 8 7 6 5 4 3 2 OR B(0) POLARITY
19 18 17 16 15 14 13 12 11
1
9
0
PLS153/A
Product specification
SP00283
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (18 x 42 x 10)
PLS153/A
SNAP RESOURCE SUMMARY DESIGNATIONS
P31 DIN153 I0 NIN153 P0 D0 D9
I7 B0 DIN153 NIN153
B9 AND CAND TOUT153 S9 X9 OR B9
S0 X0 EXOR153
B0
SP00284
October 22, 1993
9

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